Memristors have emerged as a leading nonvolatile memory solution for in-memory computing in neuromorphic systems. In particular, they are widely used in Crossbar Array (CBA) architectures to perform Vector-Matrix Multiplications (VMM). However, these configurations are susceptible to sensing accuracy issues, including sneak path currents and variability in the memristor's stored resistance values. This study focuses on an additional source of error during VMM readout in CBA-based architectures. The VMM operation is based on adding the partial multiplications of the input voltage (Vin) with the inverse of the memristor resistance (Rcell) in 1T1R cells, resulting in an output current (I). For clarity, Vin and Rcell are modeled as binary operands, yielding four possible binary multiplications. Ideally, only the 1x1 operation should contribute significantly to the output current. However, depending on the resistance window between the High Resistance State (HRS) and Low Resistance State (LRS), the 1x0 operation can also produce non-negligible currents, potentially leading to output errors. The objectives of this work are twofold: first, to analyze the consequences of this unintended current contribution from the 1x0 operation, and second, to assess its practical impact through simulation. Several CBA configurations of varying sizes are simulated to study the error magnitude and its relation to the HRS/LRS ratio, offering insights into how this effect influences the scalability of CBA architectures.