Test infrastructure for multi-core memristor-CMOS neuromorphic chip
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The advent of hybrid memristor-CMOS technologies opens an exciting alternative to implement compact neuromorphic hardware with dense layers of neurons interconnected via memristive synapses for low-power energy-efficient high-speed inference applications and online learning. Using this hybrid technology, we have fabricated a configurable and scalable multi-core architecture formed by 1k pre- and 1k post-synaptic neurons densely interconnected through 64k memristors. Given the complexity of the system, we have implemented a test infrastructure based on a SoC (System-on-Chip) platform, which deals with the digital programming and communication to configure different architectures and run experiments from a processor.